assembly - What comes after QWORD? -


if

  • 8 bits byte

  • two bytes word

  • four bytes dword

  • 8 bytes qword

what name 16 bytes?

tl:dr: in nasm, after resb/resw/resd/resq there's reso, resy, , resz. in instruction mnemonics , intel terminology (used in manuals), o (oct) , dq (double-quad) both used. dqword isn't used, oword.

disassemblers use xmmword ptr [rsi] memory operand explicit sizes in masm or .intel_syntax gnu syntax. iirc, there no instructions size isn't implied mnemonic and/or register.

note question x86-specific, , intel's terminology. in other isas (like arm or mips), "word" 32 bits, x86 terminology originated 8086.

terminology in instruction mnemonics

octword used in mnemonics x86-64 instructions. e.g. cqo sign-extends rax rdx:rax.

cmpxchg16b non-vector instruction operates on 16 bytes, intel doesn't use "oct" anywhere in description. instead, describe memory location m128. manual entry doesn't use "word"-based sizes.

sse/avx integer instructions have element-size part of mnemonic. in context, dq (double-quad) used, never o (oct). example, punpckl* instructions interleave elements half of 2 source vectors full destination vector:

  • punpcklwd: word->dword (16->32)
  • punpckldq: dword->qword (32->64)
  • punpcklqdq: 2 qwords->full 128bit register (64->128).

however, it's ever dq, not dqword. double-quadword sounds unnatural, think might used in intel manuals occasionally. sounds better if leave out "word", , "store double-quad @ location". if want attach "word" it, think oword sounds natural.

there's movdqa load/store/reg-reg moves. mercifully, when avx extended vector width 256b, kept same mnemonics , didn't call 256b version vmovqqa.

some instructions manipulating 128-bit lanes of 256-bit registers have 128 in name, vextractf128, new intel (other cmpxchg8b).

assembler directives:

from nasm manual:

3.2.1 db , friends: declaring initialized data

db, dw, dd, dq, dt, do, dy , dz used ... (table of examples)

do, dy , dz not accept numeric constants operands.

dt ten-byte x87 float. 16 bytes, dy ymmword (32 bytes), , dz 64 bytes (avx512 zmm). since don't support numeric constants initializers, guess use them string literal initalizers? more normal anyway db/dw/dd/dq comma-separated list of per-element initializers.

similarly, can reserve uninitialized space.

realarray       resq    10              ; array of ten reals  ymmval:         resy    1               ; 1 ymm register  zmmvals:        resz    32              ; 32 zmm registers

terminology in intrinsics, , avx512

as mentioned in answer on how can microsoft size of word in winapi 16 bits?, avx512's per-element masking during other operations makes naming tricky. vshuff32x4 shuffles 128b elements, masking @ 32bit element granularity.

however, intel not backing away word=16 bits. e.g. avx512bw , avx512dq put terminology right in name. intrinsics use them, previous epi32, not d. (i.e. _mm256_broadcastd_epi32(__m128i), _mm256_broadcastw_epi16(__m128i). b/w/d/q totally redundant. maybe mistake?)

(does else find asm mnemonics easier remember , type annoyingly-long intrinsics? have know asm mnemonics read compiler output, nice if intrinsics used mnemonics instead of second naming scheme.)


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