makefile - Performing an action over each source file with make -


i have created makefile this

cc = sdcc srcs = $(pname).c\     ../../src/gpio.c     ../../src/timers.c     ../../src/i2c.c $hdrs = -i../../headers  all:     mkdir -p ./output     $(cc) $(srcs) -lstm8 -mstm8 $(hdrs)

the problem is, sdcc can compile 1 source @ time. need perform foreach on each source have defined in srcs variable. how in gnu-make?

according the docs, must compile files other 1 containing main() separately, produce .rel files, include in compilation command main file. there several variations on how that. following avoids features specific gnu make:

# we're assuming posix conformance .posix:  cc = sdcc  # in case ever want different name main source file     mainsrc = $(pmain).c  # these sources must compiled .rel files: extrasrcs = \     ../../src/gpio.c \     ../../src/timers.c \     ../../src/i2c.c  # list of .rel files can derived list of source files rels = $(extrasrcs:.c=.rel)  includes = -i../../headers cflags   = -mstm8  libs     = -lstm8   # provides conventional target name "all"; optional # note: assume set pname via means not exhibited in original file all: $(pname)  # how build overall program $(pname): $(mainsrc) $(rels)     $(cc) $(includes) $(cflags) $(mainsrc) $(rels) $(libs)  # how build .rel file corresponding .c file # gnu have use pattern rule this, that's gnu-specific .c.rel:     $(cc) -c $(includes) $(cflags) $<  # suffixes appearing in suffix rules care about. # necessary because .rel not 1 of standard suffixes. .suffixes: .c .rel

if carefully, way, see file not explicitly perform looping on source files, or such thing. describes how build each target, including intermediate targets. make figures out on own how combine rules go sources final program (or other target specify among you've taught build).


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