hdl - Syntax error in if statement in vhdl -

i new vhdl. trying out code find whether bit vector is r not (using hamming weight of bit vector). code wrote is:

entity hw_mod generic( bits:integer  ); port ( inp : in std_logic_vector((bits-1) downto 0;    cout : out std_logic ); end entity hw_mod   architecture hw_arch of hw_mod begin   process(inp)  variable count : integer:=0;  begin     labelloop: in 0 (bits-1) loop                  if(inp(i)=='1')                    count:= count+1;                          end if;                       end loop;                    if ((count mod 2)== '0')                        cout:=1;                    else            cout:=0;            end if;  end process;    end hw_arch; 

the error keep getting "near "=": syntax error in 2 places.

several problems. use editor checks syntax while type.

• parentheses not matched.
• you missing semicolons,
• you use c-style comparisons (== instead of =)
• variable assignments need signals (:= instead of <=)